Back خط أنابيب تعليمات Arabic Canalització d'instruccions Catalan Pipelining Czech Pipeline (Prozessor) German Σωλήνωση (υπολογιστές) Greek Segmentación de instrucciones Spanish خط لوله (رایانه) Persian Käskykannan liukuhihna Finnish Pipeline (architecture des processeurs) French Instrukcijski cjevovod Croatian
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Clock cycle Instr. No.
|
1 | 2 | 3 | 4 | 5 | 6 | 7 |
|---|---|---|---|---|---|---|---|
| 1 | IF | ID | EX | MEM | WB | ||
| 2 | IF | ID | EX | MEM | WB | ||
| 3 | IF | ID | EX | MEM | WB | ||
| 4 | IF | ID | EX | MEM | |||
| 5 | IF | ID | EX | ||||
| (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back).
In the fourth clock cycle (the green column), the earliest instruction is in MEM stage, and the latest instruction has not yet entered the pipeline. | |||||||
In computer engineering, instruction pipelining is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps (the eponymous "pipeline") performed by different processor units with different parts of instructions processed in parallel.