| General information | |
|---|---|
| Launched | November 2007 |
| Performance | |
| Max. CPU clock rate | 1.06 GHz to 3.33 GHz |
| FSB speeds | 533 MT/s to 1600 MT/s |
| Cache | |
| L1 cache | 64 KB per core |
| L2 cache | 1 MB to 12 MB unified |
| L3 cache | 8 MB to 16 MB shared (Xeon) |
| Architecture and classification | |
| Microarchitecture | Core |
| Instruction set | x86-16, IA-32, x86-64 |
| Extensions | |
| Physical specifications | |
| Transistors |
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| Cores |
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| Sockets | |
| Products, models, variants | |
| Model |
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| History | |
| Predecessor | Core |
| Successor | Nehalem |
| Support status | |
| Unsupported | |
In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.
Architectural improvements over 65-nanometer Core 2 CPUs include a new divider with reduced latency, a new shuffle engine, and SSE4.1 instructions (some of which are enabled by the new single-cycle shuffle engine).[1]
Maximum L2 cache size per chip was increased from 4 to 6 MB, with L2 associativity increased from 16-way to 24-way. Cut-down versions with 3 MB L2 also exist, which are commonly called Penryn-3M and Wolfdale-3M as well as Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model with only one active core.