Back معمارية آرم Arabic ARM (працэсар) BE-X-OLD Advanced RISC Machines Catalan ARM Czech ARM (processorarkitektur) Danish Arm-Architektur German ARM (αρχιτεκτονική) Greek Arquitectura ARM Spanish ARM (arvutiarhitektuur) Estonian ARM arkitektura Basque
 | |
| Designer | |
|---|---|
| Bits | 32-bit, 64-bit |
| Introduced | 1985 |
| Design | RISC |
| Type | Load–store |
| Branching | Condition code, compare and branch |
| Open | Proprietary |
| Introduced | 2011 |
|---|---|
| Version | ARMv8-R, ARMv8-A, ARMv8.1-A, ARMv8.2-A, ARMv8.3-A, ARMv8.4-A, ARMv8.5-A, ARMv8.6-A, ARMv8.7-A, ARMv8.8-A, ARMv8.9-A, ARMv9.0-A, ARMv9.1-A, ARMv9.2-A, ARMv9.3-A, ARMv9.4-A, ARMv9.5-A, ARMv9.6-A |
| Encoding | AArch64/A64 and AArch32/A32 use 32-bit instructions, AArch32/T32 (Thumb-2) uses mixed 16- and 32-bit instructions[1] |
| Endianness | Bi (little as default) |
| Extensions | SVE, SVE2, SME, AES, SM3, SM4, SHA, CRC32, RNDR, TME; All mandatory: Thumb-2, Neon, VFPv4-D16, VFPv4; obsolete: Jazelle |
| Registers | |
| General-purpose | 31 × 64-bit integer registers[1] |
| Floating point | 32 × 128-bit registers[1] for scalar 32- and 64-bit FP or SIMD FP or integer; or cryptography |
| Version | ARMv9-R, ARMv9-M, ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M, ARMv6-M |
|---|---|
| Encoding | 32-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions. |
| Endianness | Bi (little as default) |
| Extensions | Thumb-2, Neon, Jazelle, AES, SM3, SM4, SHA, CRC32, RNDR, DSP, Saturated, FPv4-SP, FPv5, Helium |
| Registers | |
| General-purpose | 15 × 32-bit integer registers, including R14 (link register), but not R15 (PC) |
| Floating point | Up to 32 × 64-bit registers,[2] SIMD/floating-point (optional) |
| Version | ARMv6, ARMv5, ARMv4T, ARMv3, ARMv2 |
|---|---|
| Encoding | 32-bit, except Thumb extension uses mixed 16- and 32-bit instructions. |
| Endianness | Bi (little as default) in ARMv3 and above |
| Extensions | Thumb, Jazelle |
| Registers | |
| General-purpose | 15 × 32-bit integer registers, including R14 (link register), but not R15 (PC, 26-bit addressing in older) |
| Floating point | None |
ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of RISC instruction set architectures (ISAs) for computer processors. Arm Holdings develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licenses cores that implement these ISAs.
Due to their low costs, low power consumption, and low heat generation, ARM processors are useful for light, portable, battery-powered devices, including smartphones, laptops, and tablet computers, as well as embedded systems.[3][4][5] However, ARM processors are also used for desktops and servers, including Fugaku, the world's fastest supercomputer from 2020[6] to 2022. With over 230 billion ARM chips produced,[7][8] since at least 2003, and with its dominance increasing every year[update], ARM is the most widely used family of instruction set architectures.[9][4][10][11][12]
There have been several generations of the ARM design. The original ARM1 used a 32-bit internal structure but had a 26-bit address space that limited it to 64 MB of main memory. This limitation was removed in the ARMv3 series, which has a 32-bit address space, and several additional generations up to ARMv7 remained 32-bit. Released in 2011, the ARMv8-A architecture added support for a 64-bit address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set.[13] Arm Holdings has also released a series of additional instruction sets for different rules; the "Thumb" extension adds both 32- and 16-bit instructions for improved code density, while Jazelle added instructions for directly handling Java bytecode. More recent changes include the addition of simultaneous multithreading (SMT) for improved performance or fault tolerance.[14]
- ^ a b c Cite error: The named reference
v8archwas invoked but never defined (see the help page). - ^ "6.1.2.1 VFP register usage conventions". Procedure Call Standard for the ARM Architecture. Arm Holdings. 6 October 2023. Retrieved 22 August 2024.
- ^ Wilson, Roger (2 November 1988). "Some facts about the Acorn RISC Machine". Newsgroup: comp.arch. Retrieved 25 May 2007.
- ^ a b Hachman, Mark (14 October 2002). "ARM Cores Climb into 3G Territory". ExtremeTech. Retrieved 24 May 2018.
- ^ Turley, Jim (18 December 2002). "The Two Percent Solution". Embedded. Retrieved 14 February 2023.
- ^ Cutress, Ian (22 June 2020). "New #1 Supercomputer: Fujitsu's Fugaku and A64FX take Arm to the Top with 415 PetaFLOPs". anandtech.com. Retrieved 25 January 2021.
- ^ "Arm Partners Have Shipped 200 Billion Chips". Arm (Press release). Retrieved 3 November 2021.
- ^ "Enabling Mass IoT connectivity as ARM partners ship 100 billion chips". community.arm.com. 27 February 2017. Retrieved 8 April 2020.
the cumulative deployment of 100 billion chips, half of which shipped in the last four years. [..] why not a trillion or more? That is our target, seeing a trillion connected devices deployed over the next two decades.
- ^ "MCU Market on Migration Path to 32-bit and ARM-based Devices: 32-bit tops in sales; 16-bit leads in unit shipments". IC Insights. 25 April 2013. Retrieved 1 July 2014.
- ^ Turley, Jim (2002). "The Two Percent Solution". embedded.com.
- ^ "Arm Holdings eager for PC and server expansion". The Register. 1 February 2011.
- ^ McGuire-Balanza, Kerry (11 May 2010). "ARM from zero to billions in 25 short years". Arm Holdings. Retrieved 8 November 2012.
- ^ "ARM Discloses Technical Details of the Next Version of the ARM Architecture" (Press release). Arm Holdings. 27 October 2011. Archived from the original on 1 January 2019. Retrieved 20 September 2013.
- ^ "Announcing the ARM Neoverse N1 Platform". community.arm.com. 20 February 2019. Retrieved 8 April 2020.