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RISC-V

RISC-V
DesignerUniversity of California, Berkeley
Bits32, 64, 128
Introduced6 August 2014 (2014-08-06)[1]
Version
  • unprivileged ISA 20250508,[2]
  • privileged ISA 20250508[2]
DesignRISC
TypeLoad–store
EncodingVariable
BranchingCompare-and-branch
EndiannessLittle[3]: 9 [a]
Page size4 KiB
Extensions
  • M: Multiplication
  • A: Atomics – LR/SC & fetch-and-op
  • F: Floating point (32-bit)
  • D: FP Double (64-bit)
  • Q: FP Quad (128-bit)
  • Zicsr: Control and status register support
  • Zifencei: Load/store fence
  • C: Compressed instructions (16-bit)
  • B: Bit manipulation
  • V: Vector Operations
  • J: Interpreted or JIT-compiled language support
OpenYes, royalty free
Registers
General-purpose
  • 16
  • 32
(Includes one always-zero register)
Floating point
  • 32
(Optional; width depends on available extensions)
Vector
(Optional; width depends on hardware)[c]

RISC-V (pronounced "risk-five"[4]: 1 ) is a free and open-source instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Unlike proprietary ISAs such as x86 and ARM, RISC-V is described as "free and open" because its specifications are released under permissive open-source licenses and can be implemented without paying royalties.[5]

RISC-V was developed in 2010 at the University of California, Berkeley as the fifth generation of RISC processors created at the university since 1981.[6] In 2015, development and maintenance of the standard was transferred to RISC-V International, a non-profit organization based in Switzerland with more than 4,500 members as of 2025.[7]

As of 2025, RISC-V has become a popular architecture for microcontrollers and embedded systems, with development of higher-performance implementations targeting mobile, desktop, and server markets ongoing. The ISA is supported by several major Linux distributions, and companies such as SiFive, Andes Technology, Synopsys, Alibaba, and Raspberry Pi offer or have announced commercial systems on a chip (SoCs) that incorporate one or more RISC-V compatible CPU cores.[8]

  1. ^ Asanović, Krste; Patterson, David A. (6 August 2014). Instruction Sets Should Be Free: The Case For RISC-V (PDF). EECS Department, University of California, Berkeley. UCB/EECS-2014-146.
  2. ^ a b Cite error: The named reference techspecs was invoked but never defined (see the help page).
  3. ^ a b Cite error: The named reference isa20191213 was invoked but never defined (see the help page).
  4. ^ Cite error: The named reference isa201912132 was invoked but never defined (see the help page).
  5. ^ "Frequently Asked Questions (FAQ) – RISC-V International". Retrieved 20 August 2024.
  6. ^ Urquhart, Roddy (29 March 2021). "What Does RISC-V Stand For? A brief history of the open ISA". Systems & Design: Opinion. Semiconductor Engineering.
  7. ^ "About RISC-V". RISC-V International.
  8. ^ Cite error: The named reference :5 was invoked but never defined (see the help page).


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